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(Nikkei BP Group)

(No.1 High-Tech News Site in Japanese)

  • NEC FPGA Chips Aimed at Data Communications, Multimedia
  • February 19, 1999 (TOKYO) — NEC Corp. said it test manufactured a high-speed, dynamically reconfigurable field programmable gate array (FPGA) chip for data communications and multimedia use.
    The Dynamically Reconfigurable Logic Engine (DRLE) chip can handle data communications and multimedia data programs more than 10 times faster than conventional devices, using less power consumption, company officials said. The company positions the chip as its first step to achieve virtual hardware or a design concept for a next generation of computers.

    Dynamically reconfigurable means to change programs (circuit configuration) in the chip while its system is running and make it perform multiple processes. Programming data is stored in static random access memory (SRAM) circuits incorporated in the chip to shorten the programming time.

    U.S.-based Xilinx Inc. and other companies are already marketing dynamically reconfigurable FPGA chips, into which programming data are generally input from outside the chip. Makers of the FPGA chips design so that both the conventional outside method and internally stored method are available, because dynamically reconfigurable devices are not widely disseminated yet.

    NEC’s prototype chip is a dedicated, dynamically reconfigurable chip.

    NEC said the programming speed is more than 10,000 times as fast as that of commercialized FPGA chips. Although its chip area increased by 35 percent due to the addition of the SRAM, eight patterns of programming data are stored in the chip.

    The chip uses a 0.25-micron design rule. Its wiring is four aluminum layers. Its supply voltage is 2.5V.

    NEC said at a press conference held at its head office in Tokyo that the chip could hardly avoid Xilinx’s basic patents.

    But NEC has prospects to reach a cross-license agreement with Xilinx, because the chip incorporates many technologies developed by NEC, said Takao Nishitani, assistant general manager of NEC’s Silicon System Laboratories. NEC has applied about 20 patents, company officials said.

    Also, NEC is developing software tools to design programming data for the chip, which will be completed within a year. Combination of that software and the Cyber, a behavior synthesis tool developed by NEC, will enable programs written in C language to convert into programming data for the chip, company officials said.

    NEC released the details of the technologies at the International Solid State Circuits Conference (ISSCC ’99) held in San Francisco, Calif., from Feb. 15-17.

    More information in English is at: http://www.nec.co.jp/english/today/newsrel/9902/1502.html

    (Nikkei Electronics)

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