USB 2.0 Takes Off
The development of peripheral equipment using the USB 2.0 serial interface, a specification drawn up by a group centered around Intel Corp, is underway. With a maximum data transfer rate of 480 Mbits/s, the specification will be utilized in the consumer equipment and personal computer markets along with IEEE1394.
Vendors have begun development of new personal computers (PC) and peripherals equipped with the new Universal Serial Bus (USB) 2.0 interface, with shipments planned to begin from the end of 2000 through 2001. Some chip vendors have already begun sample-shipping integrated circuits (IC) that support USB 2.0 to peripheral equipment manufacturers.
Even with the right IC, however, there is no guarantee that development of the equipment will go as planned. In order to put USB 2.0-compliant equipment into production, a number of requirements will need to be met.
These include the development of device driver software, an implementation capable of pumping signals at stable speeds of up to 480 Mbits/s, and the verification of multi-vendor interoperability (Fig 1). If any one of these is not implemented, USB 2.0 equipment will not enjoy market success.
The slow market progress of USB 1.0 equipment is evidence of this. Intel Corp released a PC chipset with a USB 1.0-compliant interface in 1996, but USB 1.0-compliant peripherals did not begin to take hold in the market until 1998. The primary reason for this involved delays in device driver software development.
The development of drivers for USB 2.0 seems likely to go more smoothly than it did for USB 1.0, however, because many of the drivers developed for USB 1.1 can be used without modification (Fig 2). The only hitch that may slow the entire USB 2.0 project is the development of the device driver for the host controller IC. Microsoft Corp has announced that it has already received two host controller ICs, and development is proceeding smoothly.
Open Register Sets
The smooth development of the host controller IC owes much to lessons learnt by Intel from the USB 1.0 project.
Intel was firmly in the lead in the development of a host controller IC for USB 1.0, but refused to disclose details of the built-in register set, called the Universal Host Controller Interface (UHCI). As a result, Microsoft, Compaq Computer Corp, National Semiconductor Corp and other firms ended up developing a host controller equipped with a different register set, called the Open Host Controller Interface (OHCI). This meant that there were host controller chips with different register sets on the market, which caused a delay in driver development.
For the USB 2.0 specification, Intel made the decision to make the Enhanced Host Controller Interface (EHCI) register set available at no charge. This means that all the host controller ICs being developed by multiple firms use the same register set, which has benefited device driver development.
Driver Development Needed
The device drivers for peripherals (class drivers) will not, in principle, require any modifications. Microsoft, for example, will be able to use the drivers already provided with Windows. In fact, demonstrations of USB 2.0-compliant equipment by peripheral manufacturers are being made with unmodified 1.1 drivers.
Some new driver development, however, will be needed for isochronous data transfers at rates of 480 Mbits/s. For USB 2.0, the smallest unit of data transfer (microframe) is 125micro-second, or one-eighth that of USB 1.1. This means that new device drivers must be provided to implement isochronous transfer with the shorter microframes. This will be important to designers of cameras that transfer video data or to makers of audio equipment that handles voice data streams.
Microsoft has no plans to provide an isochronous transfer device driver for USB 2.0 for existing operating systems (OS), like Windows 2000 or Windows 98. The probable reason for this is that the firm wants to avoid adversely affecting driver development by creating drivers for multiple OS. The first OS to come with the driver as standard equipment will probably be the one currently in the pipeline, codenamed "Whistler."
Mother Board Design Problems
The implementation of USB 2.0 seems likely to provide challenging ground for designers, at least for those working for PC or peripheral manufacturers (Fig 3). Until now, essentially no PC-related equipment had to handle signals with the exceptionally high operating frequency of 480MHz.
To minimize signal waveform distortion and spurious electromagnetic noise in USB 2.0 equipment, designs will have to be more precise than ever. The design techniques used for USB 1.1 could actually worsen results in some cases. Subtleties in techniques applied in this area may enable certain manufacturers to ship compliant equipment more rapidly than others.
Wiring on the PC motherboard is a key problem area (Fig 4). The board area is large, which means that measures to eliminate impedance mismatches and electromagnetic interference (EMI) will be especially important. According to Intel, the current four-layer printed circuit board (PCB) can be used with USB 2.0, but "characteristic impedance will require careful investigation."
Degraded Performance Problems
To minimize EMI from connectors, many equipment manufacturers will probably stop using ferrite beads so commonly used with USB 1.1. Ferrite beads operate as lowpass filters, and, as a result, would attenuate the highfrequency components of the USB 2.0 signal when operating at 480MHz. Degradation in the signal waveform could cause a failure in operation.
In response, Intel recommends replacing ferrite beads with common mode choke coils.
If the connector is placed on a board physically separated from the motherboard, then the cable interconnecting them becomes the problem. The flat cables commonly used with PCs today might have to be replaced with shielded twisted pairs to minimize EMI.
Widespread adoption of USB 2.0-compliant equipment will require careful and thorough interconnection verification. If some equipment available on the market fails to operate in certain combinations, then the market's reception of USB 2.0 will be adversely affected.
This problem has been recognised for some time with regard to cables. A cable complying with the USB 1.1 standard can be physically connected to a USB 2.0-compliant device, but a number of cables already on the market are not fully compliant with 1.1. According to a survey by GigaTest Labs of the US, two of the 11 cables sold as USB 1.1-compliant did not satisfy specifications.
The USB Implementers Forum (USB-IF), a standardization body for the USB interface, will offer multi-vendor operability testing for cables and peripheral equipment through a third party and will provide a certification mark for passing equipment. Products with this logo are scheduled to be listed on the group's Website for public access by consumers.
Operational testing and a logo system have been in existence for some time, but there was no check to see if a detected problem was actually remedied in the final product. In other words, there was no way to determine if the logo actually meant anything for a given product.
USB-IF will, therefore, develop a new logo mark. "We plan to begin operations with the new logo from the fourth quarter of 2000," said Jason Ziller, technology initiatives manager at Intel and chairman of USB-IF.
The group is already working on certifying the third party to handle test services. Contech Research Inc and National Technical Systems (NTS) Corp, both of the US, have been certified for cable and connector testing, while Professional Interactive Media Centre NV of Belgium has been certified for peripheral equipment testing. It will still take some time, however, before these organizations are ready to offer full test services for prototypes.
The new logo will also apply to USB 1.1 products, and the entire logo mark scheme for USB 1.1-compliant products is heading toward a comprehensive review.
IC Production Imminent
USB 2.0-compliant ICs are finally shipping. Throughout summer 2000, peripheral and PC manufacturers have had to settle for field programmable gate array (FPGA) evaluation chips. However, by about the fall, actual product versions of ICs should begin to ship. This will further accelerate development of peripherals and PCs equipped with USB 2.0 interfaces.
Broadly speaking, the three types of USB 2.0-compliant ICs (Fig 5) are: the host controller IC, which is built into the PC; the peripheral IC for external storage devices, scanners, printers and other devices; and the hub IC for hubs that provide branches for the USB 2.0 interface. Shipping of evaluation and sample chips has already begun for host controller ICs and peripheral ICs.
The development of a hub IC, for which circuit complexity is enormously more complex than for USB 1.1 products, will probably lag behind that of the other chips. Shipment was acheduled to begin in the second half of 2000, but since peripheral equipment operation can be verified with only the host controller and the peripheral IC, this should pose no problem in equipment development.
Host IC Standard in PCs
The host controller IC, due on the market from the second half of this year, will single-chip controllers for both USB 2.0 and USB 1.1 (Fig 6). This is to make it possible to use device controllers developed for the 1.1 standard. If USB 2.0-compliant device drivers are not installed, the chip will function as a USB 1.1-compliant host controller. In this case, the internal port allocation circuit will connect the USB 1.1 control circuit and the physical layer.
If a USB 2.0 driver is present, the port allocation circuit will first connect the USB 2.0 control circuit and the physical layer circuit. If a USB 1.1-compliant device is detected on the interface, then the physical layer for that port only is switched over to the USB 1.1 controller.
Intel eventually plans to remove the USB 1.1 control circuit from the host controller IC, and will instead integrate a hub IC controller to make it possible to connect to equipment complying with USB 1.1.
NEC Corp is in the lead when it comes to host controller IC development. Sample shipment began in April 2000, and volume production is scheduled for this month. The firm's host controller IC has a peripheral component interconnect (PCI) bus interface, because in addition to being mounted on the motherboard, NEC wanted to make it possible to place it on a PCI-bus expansion card. It also has an internal physical layer, so no external physical layer IC is required.
Intel will not release its own chipset with a USB 2.0 host controller until 2001 at the earliest; so until then, peripherals will have to support USB 2.0 via expansion boards with host controller ICs. Such boards are already under development by Royal Philips Electronics NV, Lucent Technologies Inc of the US, and others.
Peripheral Equipment Ics
Unlike the host controller IC, which will single-chip logical and physical layer circuits from the outset, the peripheral IC will initially be manufactured in the form of multi-chip sets (Fig 7). This is because while there is a requirement for only one type of host controller IC, many types of control circuits are needed for various peripherals, such as scanners, printers and compact disk read-only memory (CD-ROM) drives.
Most of the peripheral equipment ICs to ship from the second half of 2000 will be general-purpose products designed for use with the controller IC in the actual peripheral. As a result, most of them will come with an integrated device electronics/AT adapter packet interface (IDE/ATAPI), or general-purpose bus interfaces for direct connection to microcontrollers. The use of existing control ICs will shorten the time needed to develop peripheral equipment, and because a single IC can be used with many types of peripherals, volume production should help lower costs.
The IC with an internal IDE/ATAPI interface circuit is the most common type of device. Currently under development by firms including Cypress Semiconductor Corp of the US, In-System Design Inc of the US and NEC, it will make it relatively simple to use external storage devices already provided with IDE/ATAPI interfaces, such as CD-ROM and digital video disk (DVD) drives, with USB 2.0.
The product from NetChip Technology Inc of the US has a general-purpose bus, designed for connection to the external bus of the peripheral microcontroller.
External Physical Layer IC
Some of the ICs for peripheral equipment that are to ship in the second half of 2000 will not integrate physical layer circuits since this would require additional design and testing time. As a spokesman for In-System Design said, "We considered integrating the physical layer circuit, but decided to leave it out of our first-generation product because the schedule didn't allow it."
Innovative Semiconductors Inc, which is involved in macrocell design for physical layer circuits, provided a physical layer IC for the evaluation of its macrocell technology and recently decided to volume-produce it to meet demand from logical layer IC manufacturers. Innovative Semiconductors president Nabil Takla explained, "Apparently, they want to finish debugging the digital circuitry at the logical layer IC stage before integrating any analog circuits."
If a physical layer IC is used, however, the cost will certainly be higher than for one that is integrated. "Physical layer ICs for USB 2.0 currently cost between US$2 and US$5. If the same circuits are integrated, there is an increase in the chip footprint, but the cost increase should be under a dollar," said Ed Beeman, product line architect, Greeley Hardcopy Division, Hewlett-Packard Co.
Some manufacturers are integrating physical layer circuits by enlisting help from other firms. NetChip Technology integrates their own physical layer circuit in its USB 1.1 product, but decided to contract Seiko Epson Corp to handle the design of their USB 2.0 chip, for time considerations.
The industry is moving toward standardized physical layer macrocells in an effort to promote their integration by peripheral equipment IC manufacturers. The firm, inSilicon Corp of the US, Intel and seven other companies from Japan, the US and Europe defined the USB 2.0 Transceiver Macrocell Interface (UTMI) specification for physical and logical layer interfaces in March 2000. The goal is to make it possible to design a UTMI-compliant logical layer IC, and to more easily integrate a macrocell. Under the scheme, the interface for the logical layer IC can be used for directly connecting to the physical layer circuit as well.
Lucent Technologies and Innovative Semiconductors are now developing UTMI-compliant physical layer ICs for manufacturers who eventually plan to integrate UTMI-compliant physical layer circuits.
UTMI defines both 8- and 16-bit data buses for the logical layer circuit, though it seems most IC manufacturers will likely choose the 16-bit bus. This is because a key problem regards the operating frequency of the external interface on the logical layer IC. Logical layer ICs are designed with the standard libraries from the chip manufacturer, though as one IC engineer explained, "It is not easy to run at 60MHz with the standard libraries." If the operating frequency of the external bus is dropped to 30MHz, then a 16-bit physical layer IC can be used to achieve 480 Mbits/s.
The price of 16-bit ICs is of course higher than 8-bit ICs, however, and this higher cost is due in great part to the larger number of leads on the packages. The physical layer circuit has only about 6,000 gates, so chip size is determined by the number of leads. By about 2001, when UTMI-compliant macrocells are expected to be readily available, peripheral equipment ICs will integrate the physical layer IC to minimize cost.
Hub IC Scale Doubled
Sample-shipment of hub ICs is expected to lag behind that of host controllers or peripheral equipment ICs. According to Microsoft, evaluation chips will have to be received from multiple vendors in order to verify the operation of device drivers, but the firm has been unable to obtain any hub ICs for evaluation.
The primary cause of the delay in the preparation of hub ICs is due to the split transaction function, adopted to efficiently control data transmission at 480, 12 and 1.5 Mbits/s.
A split transaction occurs when the host controller issues an access request to the hub IC for access to a USB 1.1-compliant device (Fig 8).
The host controller IC first leaves access request processing up to the hub IC, and releases the signal line for other access requests. After a short pause, it queries the hub IC to see if it is ready to reply, receiving the required data if this condition is met. In other words, the hub IC handles all data exchange processing with the USB 1.1-compliant device in place of the host controller IC. This prevents any drop in utilization efficiency of the 480 Mbits/s signal line when responding by access requests for 12 or 1.5 Mbits/s devices.
As a result of the need to support split transactions, one IC manufacturer engineer estimates that the circuit scale of the hub IC has roughly doubled in the step from USB 1.1 to USB 2.0.
by Hiroki Eda
Compaq Computer: http://www.compaq.com
Contech Research: http://www.contechresearch.com
Cypress Semiconductor: http://www.cypress.com
GigaTest Labs: http://www.gigatest.com
Innovative Semiconductors: http://www.isi96.com
In-System Design: http://www.in-system.com
Lucent Technologies: http://www.lucent.com
National Semiconductor: http://www.national.com
NetChip Technology: http://www.netchip.com
Professional Interactive Media Centre NV: http://www.pimc.de
Royal Philips Electronics NV: http://www.philips.com
Seiko Epson: http://www.epson.co.jp
USB Implementers Forum: http://www.usb.org
(September 2000 Issue, Nikkei Electronics Asia)