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[Cover Story] US Makers Ready MRAM for Post-DRAM Era

The development of non-volatile memory devices to succeed DRAM has progressed to include FeRAM, MRAM and phase-change memory. Of these devices, IBM has announced that it will commercialize MRAM, using tunneling magnetoresistive (TMR) devices, in 2004, beginning with a 256-Mbit product. Devices used for gambling range from traditional desktop computers to smartphones and tablets, providing convenient access to a wide range of games. Players enjoy the flexibility of gaming on-the-go, accessing 무료슬롯 and real-money games alike. This diverse array of devices caters to different preferences and lifestyles, enhancing the gaming experience.

The development of the next generation of non-volatile random access memory (NVRAM), which is planned to eventually replace existing dynamic random access memory (DRAM), is picking up speed (Fig 1).

Majors Join in NVRAM

In December 2000, IBM Corp announced a cooperative development plan with Infineon Technologies AG of Germany to “accelerate the transfer of magnetic random access memory (MRAM) technology from lab to fab,” according to IBM Fellow & vice president, Technology and Emerging Products, Bijan Davari. IBM Fellow, Almaden Research Center, Stuart S P Parkin said, “We will begin manufacture of 256-Mbit MRAM products in 2004.”

Motorola Inc is working furiously to catch up with IBM in MRAM development. Saied Tehrani, MRAM project manager, Physical Sciences Research Laboratories, Motorola Labs, expressed confidence that his firm will at least match IBM. He said, “The product will probably appear in 2004. Experimental data has been more than promising.”

Infineon Technologies, a major player in the memory industry, and which has been unusually quiet recently, suddenly announced the tie-up with IBM for MRAM development in December 2000, followed within a few days by a similar tie-up with Toshiba Corp for ferroelectric memory (FeRAM). Toshiba and Infineon hope to jointly produce a 32-Mbit FeRAM product by the end of 2002 for use in cell phones.

Samsung Electronics Co, Ltd is not only working hard to improve the capacity and cost of FeRAM, but has also launched R&D; efforts into MRAM devices.

Intel Corp is pioneering its own path. While it has yet to make any announcements, the firm seems to be developing a phase-change non-volatile memory based on the phase-change recording films used in optical disks. Their goal is to offer lead-compatibility with flash electrically-erasable programmable read-only memory (EEPROM).

While the types of memory being developed are different, the ultimate goal is identical. As Infineon put it, “We aim to be the first to volume-produce non-volatile memory offering capacity, cost and speed on a par with DRAM.”

The Limits of DRAM

Why are manufacturers so interested in non-volatile memory now? The major reason is that it is becoming difficult to volume-produce DRAM capacitors. This is because while transistors can be made increasingly small, capacitors must assure a fixed capacitance. While the area of the devices could have been minimized through the use of various three-dimensional (3D) shapes, there are limits (Fig 2). Capacitor aspect ratio (height to width) continues to rise, and is close to reaching the limit.

One DRAM technology development manager at Fujitsu, Ltd explained, “When the aspect ratio exceeds the range from about five to eight, fabrication becomes much more difficult and yield drops off sharply.” If existing capacitor dielectric film materials are used, then this “limiting aspect ratio” will be reached in the 0.13micron process chips, slated to enter volume production in 2001. And many in the industry figure that means it’s time to switch to NVRAM without clinging to DRAM.

There is also a variety of requirements from the integrated circuit (IC) user side.

“Instant-On” with NVRAM

Once low-cost, high-speed NVRAM memory is available, it will first be utilized to replace existing NVRAM devices, such as in cellular telephones and memory cards. After that, it will gradually spread into non-mobile equipment.

In the cellular phone sector, the major issue is the write speed of flash EEPROM. It takes over 15 minutes to write a control program into a single cell phone, posing a major obstacle to productivity, claimed a source at major cell phone manufacturer Fujitsu Ltd.

Personal computer (PC) manufacturers are also eager to get their hands on the next generation of NVRAM devices. If main memory were to use NVRAM, the computer could be used instantly after it was turned on. “If NVRAM memory becomes available with the cost and performance of DRAM, it would assure us of a major market,” said Kaoru Tosaka, senior vice president and member of the Board of NEC Solutions, NEC Corp. “As the PC user group continues to expand, there is the increasing complaint that it can’t be used instantly, unlike the television. There are some OS-related problems with instant-on PCs, but we believe they can be resolved, and that the development of NVRAM memory is absolutely essential.” In existing PCs, it takes several minutes to transfer boot data from the hard disk drive (HDD) to DRAM after the power is turned on.

If NVRAM memory is used in place of DRAM, it would at least be possible to use a number of applications immediately after boot-up. If large amounts of NVRAM memory were available, all applications might be available immediately.

Feram Production

All types of non-volatile memory, including MRAM, FeRAM and phase-change memory, use structures similar to those replacing DRAM capacitors with other elements (Table 1), which is in fact close to the structure of existing semiconductor memory. It is hardly a tricky design. FeRAM, for example, merely replaces the dielectric material used in DRAM capacitors with a ferroelectric material, while MRAM uses the tunneling magnetoresistive (TMR) devices now being considered for use in next-generation HDD heads to replace capacitors, and phase-change memory uses the phase-change layer in an optical disk instead.

Of these three, FeRAM is in the lead when it comes to products. While capacity is still only in the several Kbit-class, volume production is already underway at about two million chips a month. These products, however, suffer from the same problem as conventional DRAM: it is difficult to fabricate small capacitors. Furthermore, it is also difficult to form the ferroelectric layer, raising technical barriers to achieving large capacity and low cost, which may be greater than those facing DRAM. The largest capacity of the devices is an 8-Mbit product to be commercialized in 2001.

Most people in the industry think it will be easier to boost the capacity of MRAM than FeRAM. The TMR devices, which provide DRAM-equivalent speed and actually store the data, are smaller than transistors, raising the possibility that memory cells might become smaller than DRAM cells. The 256-Mbit chip, expected to appear in 2004, will be aimed at replacing flash EEPROM and DRAM applications (Fig 3).

According to Ovonyx, Inc of the US, phase-change memory has a key sales advantage because “it will offer the same performance as FeRAM or MRAM with fewer masks.” A phase-change film is used in the storage device, recording “1” or “0” data by making a portion of the film amorphous or crystalline. The different resistance between the two states is used to read data.(see box story “Phase-Change Memory Uses Optical Disks”)

Ovonyx entered into a technical tie-up with Intel in February 2000 for phase-change memory, followed by a joint development agreement with Italian-French firm ST Microelectronics NV in December of the same year.

Peter Rickert, P E, director of ASP Platform Management and TI Fellow, Application Specific Products at Texas Instruments Inc (TI), which is engaged in R&D; of FeRAM, said: “We’re not irrevocably tied to FeRAM; the
risks are just too great. We are looking for an NVRAM to be a major in the next five years. FeRAM uses a destructive read, so that data is rewritten each time it is read. As a result, we have doubts about how many rewrite cycles it can withstand.” There are also prospective questions about how small capacitors can be made.

Because of these considerations, Infineon believes that it is safest to develop FeRAM and MRAM in parallel. The German firm feels that FeRAM and MRAM devices will coexist in the future. As Peter Bauer, executive vice president of sales and marketing at the firm, explained, “FeRAM is ideal for use in cell phones because of its minimal power consumption. MRAM, on the other hand, is good for all types of equipment demanding large-capacity memory.” He also said, “We feel this is the time for strategic investment into technologies which will pay off in a decade or two.”

Potential Recognized

At the IEEE International Solid-State Circuits Conference (ISSCC), held in February this year, Motorola announced a 256-Kbit MRAM. This is the largest capacity of a prototype chip aimed at the consumer electronics market, and offers a short 35ns read/write time comparable with DRAM (Fig 4). The firm had announced a 512-bit MRAM at the ISSCC one year earlier, but it consisted of only the memory and basic drive circuits. The new 256-Kbit chip integrates a clock generator, write current supply, controller and other peripheral circuits needed for operation.

At ISSCC 2000, IBM presented a paper on a 1-Kbit MRAM with all peripheral circuits. The prototype chip had a read time of 3ns, and a write time of 10ns, or about the same rapid speed as static RAM (SRAM).

These announcements mark the transition from the lab to the ramp-up sequence for both firms, and at the same time demonstrate to other firms in the industry the apparent hidden potential of MRAM. In reaction, it seems, NEC and Samsung Electronics both launched full-scale MRAM R&D; efforts. At present, however, IBM and Motorola are clearly more committed.

Low Yield Concerns

Technology development engineers at Japanese semiconductor firms are a bit more critical: “Ferroelectric memory came on actively in the prototype stage, too, but it took a long time to begin volume production. The key issue is whether or not MRAM can be produced with a reasonable yield.”

When new materials are used in semiconductor production, improving yield is always a major hurdle, and manufacturing the TMR element in MRAM is said to be especially difficult. “Compared to the semiconductor memory devices we’re used to, like capacitors and metal-oxidesemiconductor field-effect transistors (MOSFET), variation in characteristics due to shape variation is much larger,” said Masao Fukuma, general manager of the Silicon Systems Research Laboratories, Systems Devices and Fundamental Research, NEC Laboratories.

With regard to TMR device geometry, the thickness of the dielectric film seems to have the greatest affect on characteristic variation. TMR devices, the storage devices for the MRAM, use dielectrics sandwiched between two ferroelectric layers (see box story “Basic MRAM Knowledge”). The resistance of the TMR device varies exponentially with the thickness of the dielectric film (Fig 5a). When the thickness of the film is increased from 0.6 to 0.7nm (about 15%), the contact resistance jumps 100% from 1 to 2 kilo ohms square micron.

Minimizing this resistance variation is a crucial key to boosting MRAM production yield, because in the MRAM the difference between “0” and “1” is determined from the resistance of the TMR device. If the difference between the resistances of the two states varies widely between devices, the system will be unable to determine the value.

Minimal resistance variation is needed not only to improve yield, but also to make high-speed read possible. This is because with resistance variation, the read time must be extended. If a variation is large, for example, the read system has to undergo the following process: first, the system measures the resistance of the TMR device, then sets the state to “0” and remeasures. The system has to compare the two values to determine whether the current value is “0” or “1.”

Film Growth Technology

According to Motorola data, the resistance of a memory cell combining MOSFETs and TMR devices is about 10 k+/-5 kilo ohms square micron. Thus, variation is +/-50% (Fig 5b). This is not acceptable.

Research is underway to find a way of assuring the uniformity of the dielectric film as one solution. R&D; into dielectric films for TMR began to be active in about 1995, and because of thickness variation, films were only able to be made between 1.0 and 1.5nm. As technology improved, this gradually dropped, reaching 0.8nm in 1997, 0.7nm in 1999 and 0.6nm in 2001.

Methods are being developed to fabricate not only thickness, but also length, and width with precision. In March 2001, major etching system manufacturer Tegal Corp of the US began shipping a reactive ion etching system for TMR devices. While this type of system had been described as essential to assure yield and productivity, the Tegal system was the first on the market. The firm is already said to have adopted a cooperative stance with several American and Japanese manufacturers.

Microfabrication Doubts

The problems have, by no means, all been resolved. Even though the immediate problems have been solved, it is still unclear whether or not microfabrication can continue to be applied to the new technologies. All conventional memory, like flash EEPROM and DRAM, have achieved increased integration by reducing the design rule, along with reductions in manufacturing cost and power dissipation. If finer design rules can make the memory cell area smaller, more chips can be cut from a single wafer, and the per-bit manufacturing cost reduced. Questions have, however, been raised as to whether this same approach will work with MRAM.

No clear-cut solutions have yet emerged, and IBM’s Parkin commented, “Unless we have some ideas about how to resolve these problems for several generations in the future, we have little intention of moving to production.” He added that they have little concept of what “further future generations” might look like.

Current dissipation may turn out to be the biggest problem. As TMR devices are made smaller through microfabrication, write current increases, and current consumption jumps accordingly, said Shuichi Tahara, senior manager, Silicon Systems Research Laboratories and Fundamental Research Laboratories, NEC System Devices and Fundamental Research. TMR devices are smaller than MOSFETs, and the memory cell area can be reduced by merely shrinking the MOSFET. At a certain level, however, the rule is so fine that interference occurs, making rewrite operations unstable.

For these reasons, research will be active in the pursuit of slashing manufacturing costs by composing memory cells of only TMR devices without any MOSFETs, and into making TMR devices that do not draw more current even when they are made smaller.

Lower Cost, Single TMR

With the cooperation of IBM, Infineon is advancing development of a method of making memory cells out of only TMR devices (Fig 6). Hewlett-Packard Co (HP) seems to be developing a similar type of MRAM.

Because TMR devices are smaller than MOSFETs, leaving out the MOSFET would mean reducing the area of the memory cell to less than half (Fig 7). It is also theoretically possible to stack memory cells on each other or on peripheral circuits. This is possible because TMR devices do not necessarily have to be grown on single crystal Si. One TMR device can be formed on top of the first, or a TMR device can be placed on top of peripheral circuits on top of the Si wafer.

For example, if two memory cells are stacked, effective memory cell area is halved because two memory cells are implemented in the area of one. If three or four cells can be stacked, then theoretically the effective size of the memory cells drops to a third, a quarter and so on.

This is exactly why Wilhelm Beinvogl, senior vice president, Technology and Innovation, Memory Products Division of Infineon believes that the “MRAM of this type is ideal for holding down manufacturing costs.” According to estimates prepared by his firm, the manufacturing cost for a three-layer chip would be about 15% less than for a NAND-type flash EEPROM (which has the smallest memory cell area of any semiconductor memory, and is used in compact memory cards and similar applications).

Read Method the Key

The idea for this type of MRAM had been around for quite a while, since before the concept of MRAM with MOSFETs was developed. Even with the smaller memory cell area, however, if the number of memory cells is increased to boost capacity, read becomes difficult. This is precisely why IBM and others began R&D; based on combinations with MOSFETs.

The difficulty stems from the various leakage currents, says Motorola’s Tehrani. With MRAM, the establishment of “0” or “1” data is made based on the resistance of the TMR device, which is normally implemented by passing current to the TMR device and detecting the output current. If the cell is made entirely of TMR devices, however, it is difficult to accurately read the data even if the current is accurately sensed. This is because the current input to the target memory cell leaks to other cells (Fig 8).

The MOSFET acts as a switch to control current applied to target memory cells, preventing current from leaking to other cells. The MOSFET for the cell to be read is turned on, and those for other memory cells are turned off.

Minimizing Current Use

Projects are also under way to shrink TMR device size while minimizing the growth in TMR device current consumption. One method is described by IBM’s Parkin as “implementing write not only with current, but also with the use of magnetic materials, coupled with modifications to the layer structure of TMR devices.”

When the TMR device is made smaller, write current rises because of the increase in the switching magnetic field. This switching field is required to reverse the magnetization of the TMR device. With MRAMs, the magnetic field is generated by a current flow, rewriting data by reversing the magnetic polarity of the TMR device. As rules shrink, this field increases in power, causing a similar increase in rewrite current.

Another possible problem that may occur when the size of the TMR device is reduced is that the switching field may vary when the magnetization of one TMR device affects the state of another.

by Motoyuki Oishi and Terue Matsumoto


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