(Nikkei BP Group)
(No.1 High-Tech News Site in Japanese)
| Sharp, Cadence to Develop IP Core for System-on-a-Chip
December 15, 1998 (TOKYO) -- Sharp Corp. said it will collaborate with
U.S.-based Cadence Design Systems Inc. to develop an Intellectual Property
core for its data-driven media processor.
|The IP core they aim to develop is intended for use in system IC or system-on-a-chip
An Intellectual Property (IP) core is basically a library of function
blocks that semiconductor manufacturers provide openly to developers
of IT equipment to help them design new devices more easily. Because
the operation of each of the function blocks has already been verified,
the time that it takes to design a system-on-a-chip can be greatly reduced
simply by putting together the required blocks from an IP core.
The DDMP is a data flow-type processor developed by Sharp and unveiled
in March 1997. Unlike ordinary von Neumann-type processors which continuously
perform operations in sync with the chip's clock signal, the DDMP stops
running whenever there is no data waiting to be processed. This makes
it ideal for use in portable and mobile IT devices, where lower power
consumption is always highly desirable.
Under the terms of the tie-up between the two companies, Sharp will first
supply Cadence with its design data for the DDMP. Then, Cadence will
use that data to construct an IP core that conforms to the virtual
socket interface (VSI) standards and which can be used with Cadence's
own microchip design tools.
When the DDMP IP core is ready, Sharp will promote it for use in microchips
which are to be incorporated in portable IT devices.
According to the company, by the end of the year 2000 it hopes it will
have received around 30 orders for designing and developing custom microchips
which incorporate the DDMP. If that is the case, Sharp estimates the
DDMP products will account for 8-10 percent of its total semiconductor
(BizTech News Dept.)
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