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(Nikkei BP Group)

(No.1 High-Tech News Site in Japanese)

  • Hitachi Unveils IC Tech for Next Mainframe Computers
  • September 30, 1998 (TOKYO) -- Hitachi Ltd. revealed details to Nikkei Microdevices of the microchip technologies for its next-generation Skyline II mainframe computer, including copper wiring for transistor interconnections.
    Copper wiring is attracting attention as a next-generation IC process technology because it can reduce IC transmission delays. Earlier this month, IBM Corp. introduced 400MHz PowerPC microprocessors using copper wiring. From the second quarter of 1999, Texas Instruments Inc. will start producing its Ultra SPARC III microprocessors (600MHz class devices) and digital signal processors with copper wiring.

    The product plan for the Skyline II was revealed when Hitachi Data Systems Corp. (HDS) of the United States announced its new S/390 compatible mainframe HDS Pilot Series.

    Hitachi revealed to Nikkei Microdevices a variety of new IC technologies.

    Hitachi will continue to use its current advanced CMOS-ECL (ACE) circuits with CMOS and emitter coupled logic (ECL). Copper wiring and silicon-on-insulator (SOI) technology will be utilized for microchips in the processor modules.

    As part of a seven-layer metal process, copper will be used for the second through seventh layers. A sputtering process will be used for the copper deposition.

    SOI wafers processed with a bonding method will be procured from Shin-Etsu Handotai Co., Ltd. The wafer price is as much as four to five times that of conventional wafers, company officials said.

    The bonding type SOI wafers will be used because a silicon layer about a micron in thickness is needed to process bipolar transistors. It is difficult for an SOI wafer processed with separation by implanted oxygen (SIMOX) technology to accept a deposit of a silicon layer of that thickness on its insulating layer (SiO2), company officials said.

    A 0.25-micron design rule will be used except for emitters of bipolar transistors, to which a 0.20-micron design rule will be applied.

    The performance per processor module of the Skyline II will increase by as much as twice that of the current model to about 280MIPS. Its configuration of modules will be raised from the current model's eight units to 12 units. And thus, its performance per system will be improved by as much as 2.7 times that of the current system.

    The Skyline II for Japan will be sold at the same time as the model for the U.S. market. It will follow the MP5800E in Japan, and the product name is not finalized yet.

    (Nikkei Microdevices)

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    Updated: Tue Sep 29 16:42:32 1998 PDT